1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor integrated circuit system using the same, and a control method of a semiconductor memory device.
2. Description of the Related Art
In recent years, electronic devices such as DVC (digital video camera) and DSC (digital still camera), cellular telephones or the like, have made significant technological advances. In association therewith, there is a growing demand for increasing the size and definition of image handled in these electronic devices. Furthermore, in order to transmit image information over a communication network, a transmission line with a sufficiently broad bandwidth (broadband) is required. However, the capacity of a memory device mounted on these electronic devices has limitations, and the bandwidth of communication channels are limited, and thus attention is focused on the compression technology to suppress the bandwidth of data itself.
Compression of moving images has been conducted by splitting a screen into a plurality of blocks to detect differences (spatial redundancy) in images between adjacent blocks, or detecting differences (temporal redundancy) in motion of images between previous and subsequent frames to remove redundant portions. In H.264 (MPEG-4AVC) and the like, a highly advanced compression algorithm is adopted, and it is desired to improve the processing speed of compression devices.
Patent Reference 1JP-A-2003-208303Patent Reference 2JP-A-08-305625Patent Reference 3JP-A-01-171191
In such moving image compression by removing redundant portions, since data of a plurality of blocks (or frames) is read out of image information written in a predetermined semiconductor memory device (semiconductor memory) to detect differences therebetween, access is made to the semiconductor memory device for many times. Thus, a problem arises that burden is increased on a control unit which controls the memory device. In order to process a large volume of data within a predetermined time period using an existing general purpose memory, there is no solution except that the operation frequency of the semiconductor memory device is increased to grow the number of times of processing per unit time. However, in this scheme, a problem arises that the design of a circuit board on which the semiconductor memory device, a control device, and the like to control the memory device are mounted becomes more difficult.
Patent Reference 1 discloses a semiconductor memory device which has an operation function unit for logical operation in every memory cell. Patent Reference 2 discloses a semiconductor memory with an operation function which operates data held in memory cells each other. Moreover, Patent Reference 3 discloses a storage element with an operation function which operates input data and data read out from a storage module, and supplies the resulting operation result data again to the storage module. However, none of the patent References disclose a technique that reduces the number of accesses to decrease the burden on the control unit and facilitates circuit board design.